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quad-channel isolator with integrated dc-to-dc converter data sheet adum5400 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2011 analog devices, inc. all rights reserved. features iso power integrated, isolated dc-to-dc converter regulated 5 v output 500 mw output power quad dc-to-25 mbps (nrz) signal isolation channels schmitt trigger inputs 16-lead soic package with >7.6 mm creepage high temperature operation: 105c maximum high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity (pending) iec 60747-5-2 (vde 0884, part 2) v iorm = 560 v peak applications rs-232/rs-422/rs-485 transceivers industrial field bus isolation power supply start-up bias and gate drives isolated sensor interfaces industrial plcs general description the adum5400 1 device is a quad-channel digital isolator with iso power?, an integrated, isolated dc-to-dc converter. based on the analog devices, inc., i coupler? technology, the dc-to-dc converter provides up to 500 mw of regulated, isolated power with 5.0 v input and 5.0 v output voltages. this architecture eliminates the need for a separate, isolated dc-to-dc converter in low power, isolated designs. the i coupler chip scale transformer technology is used to isolate the logic signals and the magnetic components of the dc-to-dc converter. the result is a small form factor, total isolation solution. the adum5400 isolator provides four independent isolation channels in two speed grades (see the ordering guide for more information). iso power uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. refer to the an-0971 application note for details on board layout recommendations. functional block diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc rect 4-channel i coupler core v dd1 reg gnd 1 v ia v ib v ic v id v ddl gnd 1 v iso gnd iso v oa v ob v oc v od v iso gnd iso adum5400 07509-001 figure 1. 1 protected by u.s. patents 5,952, 849; 6,873,065; 6,903,578; and 7,075,329.
adum5400 data sheet rev. a | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? electrical characteristics............................................................. 3 ? package characteristics ............................................................... 5 ? regulatory information............................................................... 5 ? insulation and safety related specifications ............................ 5 ? iec 60747-5-2 (vde 0884, part 2):2003-01 insulation characteristics .............................................................................. 6 ? recommended operating conditions ...................................... 6 ? absolute maximum ratings............................................................ 7 ? esd caution.................................................................................. 7 ? pin configuration and function descriptions..............................8 ? typical performance characteristics ..............................................9 ? terminology .................................................................................... 11 ? applications information .............................................................. 12 ? pcb layout ................................................................................. 12 ? emi considerations................................................................... 12 ? propagation delay parameters ................................................. 13 ? dc correctness and magnetic field immunity..................... 13 ? power consumption .................................................................. 14 ? power considerations................................................................ 14 ? thermal analysis ....................................................................... 15 ? insulation lifetime ..................................................................... 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 16 ? revision history 9/11rev. 0 to rev. a changes to features section............................................................ 1 changes to table 1............................................................................ 3 added table 2 and table 3; renumbered sequentially ............... 3 added table 4.................................................................................... 4 changes to table 5, table 6, and table 7 ....................................... 5 changed din v vde v 0884-10 to iec 60747-5-2 (vde 0884, part 2) throughout........................................................................... 6 changes to table 8 and table 9....................................................... 6 changes to table 11.......................................................................... 7 added figure 9; renumbered sequentially .................................. 9 changes to applications information section............................ 12 change to figure 16 ....................................................................... 14 10/08revision 0: initial version
data sheet adum5400 rev. a | page 3 of 16 specifications electrical characteristics 4.5 v v dd1 5.5 v; each voltage is relative to its respective ground. all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = 5.0 v, v iso = 5.0 v. table 1. dc-to-dc converter static specifications parameter symbol min typ max unit test conditions/comments dc-to-dc converter supply setpoint v iso 4.7 5.0 5.4 v i iso = 0 ma line regulation v iso(line) 1 mv/v i iso = 50 ma, v dd1 = 4.5 v to 5.5 v load regulation v iso(load) 1 5 % i iso = 10 ma to 90 ma output ripple v iso(rip) 75 mv p-p 20 mhz bandwidth, c bo 1 = 0.1 f||10 f, i iso = 90 ma output noise v iso(noise) 200 mv p-p c bo 1 = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz output supply current i iso(max) 100 ma v iso > 4.5 v efficiency at i iso (max) 34 % i iso = 100 ma i dd1 , no v iso load i dd1(q) 19 30 ma i dd1 , full v iso load i dd1(max) 290 ma 1 c bo = capacitive bypass output. this represents the parallel combination of high frequency bypass capacitors between pin 15 and pi n 16. table 2. dc-to-dc converte r dynamic specifications 1 mbps a grade, c grade 25 mbpsc grade parameter symbol min typ max min typ max unit test conditions/comments supply current input i dd1 19 64 ma no v iso load available to load i iso(load) 100 89 ma table 3. switching specifications a grade c grade parameter symbol min typ max min typ max unit test conditions/comments switching specifications maximum data rate 1 25 mbps within pwd limit propagation delay t phl , t plh 55 100 45 60 ns 50% input to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c minimum pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 15 ns between any two units channel-to-channel matching t pskcd /t pskod 50 6 ns
adum5400 data sheet rev. a | page 4 of 16 table 4. input and output characteristics parameter symbol min typ max unit test conditions/comments dc specifications logic high input threshold v ih 0.7 v dd1 v logic low input threshold v il 0.3 v dd1 v logic high output voltages v oh v iso ? 0.3 5.0 v i ox = ?20 a, v ix = v ixh v iso ? 0.5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v ddl , v iso supplies positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v input currents per channel i i ?20 +0.01 +20 a 0 v v ix v ddx ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 |cm| is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.7 v dd1 or 0.7 v iso for a high output or v o < 0.3 v dd1 or 0.3 v iso for a low output. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
data sheet adum5400 rev. a | page 5 of 16 package characteristics table 5. parameter symbol min typ max unit test conditions/comments resistance and capacitance resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 3 1 this device is considered a 2-terminal device; pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the thermal analysis sectio n for thermal model definitions. regulatory information the adum5400 is approved by the organizations listed in tabl e 6 . refer to table 11 and to the insulation lifetime section for details regarding the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. table 6. ul 1 csa vde (pending) 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to iec 60747-5-2 (vde 0884 part 2):2003-01 2 single protection, 2500 v rms isolation voltage testing was conducted per csa 60950-1-07 and iec 60950-1 2 nd ed. at 2.5 kv rated voltage. basic insulation at 600 v rms (848 v peak) working voltage. reinforced insulation at 250 v rms (353 v peak) working voltage. basic insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each adum5400 is proof tested by applying an insulation test voltage 3000 v rms for 1 second (current leakage detectio n limit = 10 a). 2 in accordance with iec 60747-5-2 (vde 0884 part 2):2003-01, each adum5400 is proof tested by a pplying an insula tion test volta ge 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the * marking branded on the component designates iec 60747-5-2 (vde 0884 part 2):2003-01 approval. insulation and safety related specifications table 7. critical safety-related di mensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1 minute duration minimum external air gap l(i01) 8.0 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.6 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 material group iiia material group (din vde 0110, 1/89, table 1)
adum5400 data sheet rev. a | page 6 of 16 iec 60747-5-2 (vde 0884, part 2):2003- 01 insulation characteristics the adum5400 is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the asterisk (*) marking on the package denotes iec 60747-5-2 (vde 0884, part 2) approval. table 8. vde characteristics description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 1050 v peak input-to-output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 840 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 672 v peak highest allowable overvoltage v iotm 4000 v peak withstand isolation voltage 1 minute withstand rating v iso 2500 v rms surge isolation voltage v peak = 6 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2 ) case temperature t s 150 c side 1 i dd1 current i s1 555 ma insulation resistance at t s v io = 500 v r s >10 9 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) 07509-003 figure 2. thermal derating curve, dependence of safety li miting values on case temperature, per din en 60747-5-2 recommended operat ing conditions table 9. parameter symbol min max unit operating temperature range t a ?40 +105 c supply voltages 1 v dd 4.5 5.5 v 1 each voltage is relative to its respective ground.
data sheet adum5400 rev. a | page 7 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 10. parameter rating storage temperature (t st ) ?55c to +150c ambient operating temperature (t a ) ?40c to +85c supply voltages (v dd1 , v iso ) 1 ?0.5 v to +7.0 v v iso supply current 2 ?40c to +85c 100 ma ?40c to +105c 60 ma input voltage (v ia , v ib , v ic , v id ) 1, 3 ?0.5 v to v ddi + 0.5 v output voltage (v oa , v ob , v oc , v od ) 1, 3 ?0.5 v to v iso + 0.5 v average output current per data output pin 4 ?10 ma to +10 ma common-mode transients 5 ?100 kv/s to +100 kv/s 1 each voltage is relative to its respective ground. 2 v iso provides current for dc and dynamic loads on the side 2 i/o channels. this current must be included when determining the total v iso supply current. 3 v dd1 and v iso refer to the supply voltages on the input and output sides of a given channel, respectively. see the section. pcb layout 4 see for maximum rated current values for various temperatures. figure 2 5 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 11. maximum continuous working vo ltage supporting 50-year minimum lifetime 1 parameter max unit applicable certification ac voltage, bipolar waveform 424 v peak all certifications, 50 year operation ac voltage, unipolar waveform basic insulation 600 v peak working voltage per iec 60950-1 reinforced insulation 353 v peak working voltage per iec 60950-1 dc voltage basic insulation 600 v peak working voltage per iec 60950-1 reinforced insulation 353 v peak working voltage per iec 60950-1 1 refers to the continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime sect ion for more information.
adum5400 data sheet rev. a | page 8 of 16 pin configuration and fu nction descriptions v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 v ddl 7 v iso 10 gnd 1 8 gnd iso 9 adum5400 top view (not to scale) 07509-004 figure 3. pin configuration table 12. pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage, 4.5 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 v ddl logic power supply voltage. this pin must be connected to v dd1 and have a dedicated bypass capacitor. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10, 16 v iso secondary supply voltage output for external loads, 5. 0 v. these pins are not tied together internally and must be connected together on the pcb. 11 v od logic output d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. table 13. truth table (positive logic) v ix input 1 v dd1 /v ddl state v dd1 /v ddl input (v) v iso state v iso output (v) v ox output 1 operation high powered 5.0 powered 5.0 high normal operation, data is high low powered 5.0 powered 5.0 low normal operation, data is low 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d).
data sheet adum5400 rev. a | page 9 of 16 typical performance characteristics each voltage is relative to its respective ground; all typical specifications are at t a = 25c. 0 5 10 15 20 25 30 35 40 0 0.02 0.04 0.06 0.08 0.10 0.12 output current (a) efficiency (%) 5v in/5v out 07509-005 figure 4. typical power supply efficiency at 5 v/5 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.02 0.04 0.06 0.08 0.10 0.12 i iso (a) power dissipation (w) v dd1 = 5v, v iso = 5v 07509-006 figure 5. typical total power dissipation vs. i iso with data channels idle 0 0.02 0.04 0.06 0.08 0.10 0.12 0 0.05 0.10 0.15 0.20 0.25 0.35 0.30 input current (a) output current (a) 5v in/5v out 07509-007 figure 6. typical isolated output supply current, i iso , as a function of external load, no dynamic current draw at 5 v/5 v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3 .5 4.0 4 .5 5.0 5 .5 6.0 6 .5 input voltage (v) input cur r ent (a) power (w) i dd power 07509-008 figure 7. typical short-circuit input current and power vs. v dd1 supply voltage output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load 07509-009 figure 8. typical v iso transient load response, 5 v output, 10% to 90% load step time (ms) v iso (v) 7 6 5 4 3 2 1 0 ? 1012 3 90% load 10% load 07509-027 figure 9. typical v iso = 5 v, output voltage startup transient at 10% and 90% load
adum5400 data sheet rev. a | page 10 of 16 bw = 20mhz (400ns/div) 5v output ripple (10mv/div) 07509-011 figure 10. typical v iso = 5 v output voltage ripple at 90% load 0 1.0 0.5 1.5 2.0 2.5 3.0 051 01 5 data rate (mbps) supply current (ma) 20 25 5v 07509-016 figure 11. typical i iso(d) dynamic supply current per output (15 pf output load) 0 4 8 12 16 20 051 01 5 data rate (mbps) supply current (ma) 20 25 5v in/5v out 0 7509-013 figure 12. typical i ch supply current per forward data channel (15 pf output load)
data sheet adum5400 rev. a | page 11 of 16 terminology i dd1(q) i dd1(q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operating below 2 mbps, requiring no additional dynamic supply current. i dd1(max) i dd1(max) is the input current under full dynamic and v iso load conditions. t phl propagation delay t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. propagation delay skew (t psk ) t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. channel-to-channel matching channel-to-channel matching is the absolute value of the difference in propagation delays between two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
adum5400 data sheet rev. a | page 12 of 16 applications information the dc-to-dc converter section of the adum5400 works on principles that are common to most modern power supplies. it has a secondary side controller architecture with isolated pulse- width modulation (pwm) feedback. v dd1 power is supplied to an oscillating circuit that switches current into a chip scale air core transformer. power transferred to the secondary side is rectified and regulated to 5 v. the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. the adum5400 implements undervoltage lockout (uvlo) with hysteresis on the v dd1 , v ddl , and v iso power supplies. this feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates. pcb layout the adum5400 digital isolator with integrated 0.5 w iso power dc-to-dc converter requires no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 13 ). note that a low esr bypass capacitor is required between pin 1 and pin 2, within 2 mm of the chip leads. the power supply section of the adum5400 uses a 180 mhz oscillator frequency to efficiently pass power through its chip scale transformers. in addition, normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required and must provide transient suppression at several operating frequencies. noise suppression requires a low inductance, high frequency capacitor that is effective at 180 mhz and 360 mhz. ripple suppression and proper regulation require a large value capacitor to provide bulk current at 625 khz. these are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 . the smaller capacitor must have low esr; for example, use of a ceramic capacitor is advised. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. consider a bypass capacitor between pin 1 and pin 8 and between pin 9 and pin 16 unless both common ground pins are connected together close to the package. v dd1 gnd 1 v ia v ib v iso gnd iso v oa v ob v ic v oc v id v ddl v od v iso gnd 1 bypass < 2mm gnd iso 07509-017 adum5400 figure 13. recommended pcb layout in applications involving high common-mode transients, ensure that board capacitive coupling across the isolation barrier is minimized. furthermore, design the board layout so that any coupling that does occur affects all pins on a given component side equally. failure to ensure this can cause differential voltages between pins, exceeding the absolute maximum ratings for the device (specified in table 10 ) and thereby leading to latch-up and/or permanent damage. the adum5400 is a power device that dissipates about 1 w of power when fully loaded and running at maximum speed. because it is not possible to apply a heat sink to an isolation device, the device depends primarily on heat dissipation into the pcb through the gnd pins. if the device is used at high ambient temperatures, provide a thermal path from the gnd pins to the pcb ground plane. the board layout in figure 13 shows enlarged pads for pin 8 (gnd 1 ) and pin 9 (gnd iso ). large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. multiple vias in the thermal pads can significantly reduce temper- atures inside the chip. the dimensions of the expanded pads are at the discretion of the designer and depend on the available board space. emi considerations the dc-to-dc converter section of the adum5400 components must operate at a very high frequency to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. see www.analog.com for the most current pcb layout recommendations specifically for the adum5400.
data sheet adum5400 rev. a | page 13 of 16 propagation delay parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 14 ). the propagation delay to a logic low output may differ from the propagation delay to a logic high output. input ( v ix ) output (v ox ) t plh t phl 50% 50% 07509-018 figure 14. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single adum5400 component. propagation delay skew refers to the maximum amount that the propagation delay differ s between multiple adum540x components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the trans- former. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state by the watchdog timer circuit. this situation should occur in the adum5400 only during power-up and power-down operations. the limitation on the adum5400 magnetic field immunity is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3.3 v operating condition of the adum5400 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus estab- lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt ) ? r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum5400 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 15 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 07509-019 figure 15. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), the received pulse is reduced from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum5400 transformers. figure 16 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 16 , the adum5400 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for example, at a magnetic field frequency of 1 mhz, a 0.5 ka current placed 5 mm away from the adum5400 is required to affect the operation of the component. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 07509-020 figure 16. maximum allowable current for various current-to-adum5400 spacings
adum5400 data sheet rev. a | page 14 of 16 note that in the presence of strong magnetic fields and high frequencies, any loops formed by pcb traces may induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. exercise care in the layout of such traces to avoid this possibility. power consumption the v dd1 power supply input provides power to the i coupler data channels, as well as to the power converter. for this reason, the quiescent currents drawn by the data converter and the primary and secondary i/o channels cannot be determined separately. all of these quiescent power demands have been combined into the i dd1(q) current, as shown in figure 17 . the total i dd1 supply current is equal to the sum of the quiescent operating current; the dynamic current due to high data rate, and any external i iso load. converter primary converter secondary primary data i/o 4-channel i ddp(d) e secondary data i/o 4-channel i iso(d) i iso i dd1 0 7509-021 figure 17. power consumption within the adum5400 dynamic i/o current is consumed only when operating a channel at speeds higher than the refresh rate of f r . the dynamic current of each channel is determined by its data rate. figure 12 shows the current for a channel in the forward direction, meaning that the input is on the v dd1 side of the part. the following relationship allows the total i dd1 current to be calculated: i dd1 = ( i iso v iso )/( e v dd1 ) + i chn ; n = 1 to 4 (1) where: i dd1 is the total supply input current. i chn is the current drawn by a single channel determined from figure 12 . i iso is the current drawn by the secondary side external load. e is the power supply efficiency at 100 ma load from figure 4 at the v iso and v dd1 condition of interest. the maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. i iso(load) = i iso(max) ? i iso(d)n ; n = 1 to 4 (2) where: i iso(load) is the current available to supply an external secondary side load. i iso(max) is the maximum external secondary side load current available at v iso . i iso(d)n is the dynamic load current drawn from v iso by an output channel, as shown in figure 11 . the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the additional current must be included in the analysis of i dd1 and i iso(load) . power considerations the adum5400 power input, the data input channels on the primary side, and the data output channels on the secondary side are all protected from premature operation by uvlo circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive, and all input channel drivers and refresh circuits are idle. outputs are held in a low state to prevent transmission of undefined states during power- up and power-down operations. during application of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. the primary side input channels sample the input and send a pulse to the inactive secondary output. as the secondary side converter begins to accept power from the primary, the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data, either from a logic transition or a dc refresh cycle, is received from the corresponding primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate to the primary side input. the dc-to-dc converter section goes through its own power-up sequence. when uvlo is reached, the primary side oscillator also begins to operate, transferring power to the secondary power circuits. the secondary v iso voltage is below its uvlo limit at this point; the regulation control signal from the secondary is not being generated. the primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. this creates a large inrush current transient at v dd1 . when the regulation point is reached, the regulation control circuit produces the regulation control signal that mod- ulates the oscillator on the primary side. the v dd1 current is reduced and is then proportional to the load current. the inrush current is less than the short-circuit current shown in figure 7 . the duration of the inrush depends on the v iso load conditions and the current available at the v dd1 pin. because the rate of charge of the secondary side is dependent on load conditions, the input voltage, and the output voltage level selected, ensure that the design allows the converter to stabilize before valid data is required.
data sheet adum5400 rev. a | page 15 of 16 when power is removed from v dd1 , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side hold the last state that they received from the primary until one of these events occurs: bipolar ac voltage is the most stringent environment. a 50-year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by analog devices. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 11 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases. ? the uvlo level is reached and the outputs are placed in their high impedance state. ? the outputs detect a lack of activity from the inputs and the outputs transition to their default low state until the secondary power reaches uvlo and the outputs transition to their high impedance state. any cross-insulation voltage waveform that does not conform to figure 19 or figure 20 should be treated as a bipolar ac wave- form, and its peak voltage limited to the 50-year lifetime voltage value listed in table 11 . thermal analysis the adum5400 consists of four internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the die are treated as a thermal unit, with the highest junction temperature reflected in the ja from tabl e 5 . the value of ja is based on measurements taken with the part mounted on a jedec standard 4-layer board with fine width traces and still air. under normal operating conditions, the adum5400 operates at full load up to 85c and at derated load up to 105c. the voltage presented in figure 20 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 07509-022 figure 18. bipolar ac waveform insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insu- lation degradation depends on the characteristics of the voltage waveform applied across the insulation. analog devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the adum5400. 0v rated peak voltage 07509-024 figure 19. dc waveform accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined, allowing calcu- lation of the time to failure at the working voltage of interest. table 11 summarizes the peak voltages for 50 years of service life in several operating conditions. in many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. operation at working voltages higher than the service life voltage listed can lead to premature insulation failure. 0v rated peak voltage 07509-023 figure 20. unipolar ac waveform the insulation lifetime of the adum5400 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 18 , figure 19 , and figure 20 illustrate these different isolation voltage waveforms.
adum5400 data sheet rev. a | page 16 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 21. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range package description package option adum5400arwz 4 0 1 100 40 ?40c to +105c 16-lead soic_w rw-16 adum5400crwz 4 0 25 60 6 ?40c to +105c 16-lead soic_w rw-16 1 z = rohs compliant part. 2 tape and reel are available. the addition of an rl suffix designates a 13 (1,000 units) tape and reel option. ?2008C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07509-0-9/11(a)

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